Register Interface

From Comp519

Contents 1 Register chain 2 Meaning of address bits 3 Individual register interface signals (width) 4 Other notes 5 Example timing diagrams

Register chain

• The user datapath (UDP) register interface is set up as a register chain. This allows the registers to be accessed both by software or by other modules in hardware.
  • In order to preserve the register chain, each module connected to the chain is responsible for passing along the signals to the next module in the chain. If the current module is the target of the request, then it must raise the reg_ack signal so that other modules know that the request has been handled.

Meaning of address bits

• Once a register request is received by the hardware, there are four major areas in the hardware that the request can end up: the core, SRAM, DRAM, or the user data path (UDP).
  • Your project will deal only with UDP requests. 8MB of UDP registers are allowed in the address space. Because of this, the 24th LSB of an address is set to 1 by the software to designate a UDP request. Once the hardware identifies it as a UDP request, the UDP passes along only the lower 23 bits of the address.
  • More details can be found in the file /exports/provided/NF2/lib/verilog/common/src21/NF_2.1_defines.v and udp_defines.v
• The remaining 23 bits are broken down as follows
  • The first 5 bits are a tag to say which class of UDP register your block belongs to. For the switch, this tag is all zeroes
  • For the switch, the next 12 bits identify which module is responsible for handling the request
  • For the switch, the final 6 bits identify the individual register given by the address
• These addresses are shifted to the left two bits when viewed by the software. That way, software believes that these registers are word-addressable.

Individual register interface signals (width)

reg_req (1)

When this signal is high, your output port lookup module has received a register interface request. This is the only cycle that the other register interface signals are valid.

reg_ack (1)

If low, no other modules have handled this register request. Ignore the register request if this signal is high. If your module is responsible for handling the register request, make sure to set this signal to high when you pass along the reg_req signal.

reg_rd_wr_L (1)

0 means this is a write request; 1 means this is a read request.

reg_addr_in (23)

This is the UDP address of the register request.

reg_data (32)

On a read, this signal should be filled in by the appropriate module with the requested register data. On a write, this is the data that is to be written to the register by the software.

reg_src (2)

Used to identify the source of the register request (hw or sw, I believe). You don't need to modify this during the course of the project, so pass it along in the same form that it is received.

Other notes

• Each of these signals must be forwarded to the output of the output port lookup module to preserve the register chain.
• The above signal widths are from the perspective of the output_port_lookup module.
• Switch registers:
  • Address bits 22:6 should match 0x1 in the hardware to match with the switch block (or the IP router block). Use the lower 6 bits to identify which specific register is being accessed.
  • Technically, bits 22:6 (the tag and block address fields) should match `OP_LUT_BLOCK_TAG for the switch
• Router registers:
  • Address bits 22:5 (the tag and extended block address fields) should match `OP_LUT_NON_CNTR_BLOCK_TAG for the following registers (all begin with the prefix "ROUTER_OP_LUT_", basically all the registers that are not counters):
    • ARP_MAC_HI_REG, ARP_MAC_LO_REG, ARP_NEXT_HOP_IP_REG, ARP_LUT_RD_ADDR_REG, ARP_LUT_WR_ADDR_REG, RT_IP_REG, RT_MASK_REG, RT_NEXT_HOP_IP_REG, RT_OUTPUT_PORT_REG, RT_LUT_RD_ADDR_REG, RT_LUT_WR_ADDR_REG, MAC_0_HI_REG, MAC_0_LO_REG, MAC_1_HI_REG, MAC_1_LO_REG, MAC_2_HI_REG, MAC_2_LO_REG, MAC_3_HI_REG, MAC_3_LO_REG, DST_IP_FILTER_IP_REG, DST_IP_FILTER_RD_ADDR_REG, DST_IP_FILTER_WR_ADDR_REG
  • Address bits 22:5 (the tag and extended block address fields) should match `OP_LUT_CNTR_BLOCK_TAG for the following registers (all begin with the prefix "ROUTER_OP_LUT_", basically all the registers that are counters):
    • ARP_NUM_MISSES_REG, LPM_NUM_MISSES_REG, NUM_CPU_PKTS_SENT_REG, NUM_BAD_OPTS_VER_REG, NUM_BAD_CHKSUMS_REG, NUM_BAD_TTLS_REG, NUM_NON_IP_RCVD_REG, NUM_PKTS_FORWARDED_REG, NUM_WRONG_DEST_REG, NUM_FILTERED_PKTS_REG

Example timing diagrams

• Register Read:

• Register Write: